The present invention relates generally to memory systems and in particular to systems and methods for programming, erasing and verifying sectors of bits in an electronic flash memory device having dual bit memory transistor cells operating in a single bit mode.
Flash memory is a type of electronic memory media which can be rewritten and hold its content without power. Flash memory devices generally have life spans from 100K to 300K write cycles. Unlike dynamic random access memory (DRAM) and static random access memory (SRAM) memory chips, in which a single byte can be erased, flash memory is typically erased and written in fixed multi-bit blocks or sectors. Evolving out of electrically erasable read only memory (EEPROM) chip technology, which can be erased in place, flash memory is less expensive and more dense. This new category of EEPROMs has emerged as an important non-volatile memory which combines the advantages of EPROM density with EEPROM electrical erasability.
Conventional flash memories are constructed in a cell structure wherein a single bit of information is stored in each cell. In such single bit memory architectures, each cell typically includes a metal oxide semiconductor (MOS) transistor structure having a source, a drain, and a channel in a substrate or P-well, as well as a stacked gate structure overlying the channel. The stacked gate may further include a thin gate dielectric layer (sometimes referred to as a tunnel oxide) formed on the surface of the P-well. The stacked gate also includes a polysilicon floating gate overlying the tunnel oxide and an interpoly dielectric layer overlying the floating gate. The interpoly dielectric layer is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer. Lastly, a polysilicon control gate overlies the interpoly dielectric layer.
The control gate is connected to a word line associated with a row of such cells to form sectors of such cells in a typical NOR configuration. In addition, the drain regions of the cells are connected together by a conductive bit line. The channel of the cell conducts current between the source and the drain in accordance with an electric field developed in the channel by the stacked gate structure. In the NOR configuration, each drain terminal of the transistors within a single column is connected to the same bit line. In addition, each flash cell has its stacked gate terminal connected to a different word line, while all the flash cells in the array have their source terminals connected to a common source terminal. In operation, individual flash cells are addressed via the respective bit line and word line using peripheral decoder and control circuitry for programming (writing), reading or erasing functions.
Such a single bit stacked gate flash memory cell is programmed by applying a voltage to the control gate and connecting the source to ground and the drain to a predetermined potential above the source. A resulting high electric field across the tunnel oxide leads to a phenomena called xe2x80x9cFowler-Nordheimxe2x80x9d tunneling. During this process, electrons in the core cell channel region tunnel through the gate oxide into the floating gate and become trapped in the floating gate since the floating gate is surrounded by the interpoly dielectric and the tunnel oxide. As a result of the trapped electrons, the threshold voltage of the cell increases. This change in the threshold voltage (and thereby the channel conductance) of the cell created by the trapped electrons is what causes the cell to be programmed.
In order to erase a typical single bit stacked gate flash memory cell, a voltage is applied to the source, and the control gate is held at a negative potential, while the drain is allowed to float. Under these conditions, an electric field is developed across the tunnel oxide between the floating gate and the source. The electrons that are trapped in the floating gate flow toward and cluster at the portion of the floating gate overlying the source region and are extracted from the floating gate and into the source region by way of Fowler-Nordheim tunneling through the tunnel oxide. As the electrons are removed from the floating gate, the cell is erased.
In conventional single bit flash memory devices, an erase verification is performed to determine whether each cell in a block or set of such cells has been properly erased. Current single bit erase verification methodologies provide for verification of bit or cell erasure, and application of supplemental erase pulses to individual cells which fail the initial verification. Thereafter, the erased status of the cell is again verified, and the process continues until the cell or bit is successfully erased or the cell is marked as unusable.
Recently, dual bit flash memory cells have been introduced, which allow the storage of two bits of information in a single memory cell. The conventional programming and erase verification methods employed with single bit stacked gate architectures are not adequate for such dual bit devices. Recently, dual bit flash memory structures have been introduced that do not utilize a floating gate, such as an ONO flash memory device that employs a polysilicon layer over the ONO layer for providing wordline connections. Conventional techniques do not address the characteristics associated with these types of devices. Therefore, there is an unmet need in the art for new and improved programming methods and erase verification methods and systems, which ensure proper programming and erasure of data bits in a dual bit memory architecture, and which account for the structural characteristics thereof.
A system and methodology is provided for verifying erasure of one or more dual bit cells in a memory device, such as a flash memory, operating in a single bit mode. The invention allows for efficient and thorough erasure verification, which minimizes data retention and over-erase issues particular to the ONO dual bit cell architecture operated in the single bit mode. The invention provides significant advantages when employed in association with dual bit memory cells (e.g., an ONO architecture) wherein only one bit thereof is actively used for data storage and visible to the customer. However, it will be recognized that the invention finds utility in association with dual bit memory cell architectures generally, and that the invention is thus not limited to any particular dual bit cell usage implementation or configuration. Although, only a normal bit of a dual memory cell is programmed, residual charge is accumulated into the central region of the cell which cannot be erased by normal erasure of the normal bit. Therefore, the system and methodology includes verifying and erasure of both a normal bit and a complimentary bit of the cell which are opposite sides of the same ONO transistor. The erase pulse of the normal bit is for a longer duration than the complimentary bit, since the erase pulse of the complementary bit is performed to remove only residual charge caused by the programming of the normal bit.
In one aspect of the invention, a system and method is provided for verify erasure of a memory array of dual bit flash memory cells operating in a single bit mode. The system and method include preprogramming of bits in normal bit column locations and then verify erasure of both bits in normal and complimentary bit column locations. The process of erase requires that both the normal and complimentary bits of the same transistor pass the erase verify before moving to the next transistor. Alternatively, the erase verify can be performed on a I/O or word of bits such that the normal bits and complimentary bits of an I/O have to pass before moving on to the next I/O or word. If a bit(s) in a normal bit location is not below a maximum VT defining a blank state, an erase pulse is applied to bits in normal column locations for a specified duration. A verify erasure is then performed on a bit(s) in a complimentary bit location opposite the previously tested bit(s) in the normal bit location. If the bit(s) in the complementary location is not below a maximum VT defining a blank cell, an erase pulse is applied to the bits in complimentary column locations for a specified duration. The steps of verifying and erasure are repeated until each normal bit and complimentary bit in a sector are below the maximum VT defining a blank cell. The steps are then repeated for each sector.
The normal bits are then evaluated to determine if the bits have been over-erased or fall below a minimum VT defining a blank cell. A soft program pulse is provided for the normal bits if it is determined that bits have been over-erased. The soft program verify should include a low level source voltage to shutoff the leakage from other cells on the same column. The complimentary bits are then evaluated to determine if the bits have been over-erased or fall below a minimum VT defining a blank cell. A soft program pulse is provided for the complimentary bits if it is determined that bits have been over-erased. A second or final routine of verify erasure is performed on both the bits in the normal column locations and the complimentary column locations to assure that the soft program pulse did not cause the bits to rise above the maximum VT defining a blank cell.
In another aspect of the invention, the above system and methodology for performing verify erasure comprises applying an erase pulse that provides a substantially high electric field to each I/O (an I/O being a word of memory such as 8 bits, 16 bits, 32 bits) in a sector one at a time. This operation is important for single power supply devices since the beginning of erase band to band currents for the entire array are larger than can be supplied by drain pumps. For example, an electrical field of greater than 5.0 Megavolts/cm2 ((drain voltage+|gate voltage|)*100/Tox) may be utilized for long term stable erase over cycling. After the first erase pulse, the erase verify routine can be performed on all the IO""s together. In one particular example, a Vdrain voltage is selected to be at a substantially high positive voltage (e.g., 5.5-6 Volts) and the value of Vgate voltage is at a substantially high negative voltage (e.g., |Vg| greater than |xe2x88x925.5|) where the voltage potential between Vdrain and Vgate is also a substantially high voltage (e.g., Vdiff=11-12 Volts). The above erase voltages were found adequate to provide the high electrical field to ensure adequate erase of the dual bit memory cells over a large number of cycles.
In another aspect of the invention, programming of the normal bits of the memory array are accomplished by programming at a substantially high delta VT (e.g., 2.0-3.0 V). The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses (e.g., 100-250xc2x0 C.) and/or customer operation over substantial periods of time. Furthermore, by utilizing substantially high gate and drain voltages during programming (e.g., Vgate=9.5-10.0 V and Vdrain=5.5-6.0 V), programming times are kept short (e.g., 1 microsecond) without degrading charge loss. A methodology is provided that determines the charge loss for single bit operation during program and erase cycles (e.g., 100K PE cycles). The charge losses over cycling and stress are then utilized to determine an appropriate delta VT to be programmed into a command logic and state machine. The combination of the new erase methodology, programming methodology and correctly selected delta VT facilitate control of the charge loss.
In yet another aspect of the invention, the above discussed substantially higher delta VT and gate and drain voltages are employed in a program and erase cycle. The program and erase cycle performs verify erasure by first programming the normal bits of the dual bit array utilizing the substantially higher delta VT and applying an erase pulse that provides a substantially high electric field to each I/O in a sector one at a time. After the first erase pulse, the erase verify routine is performed on all the IO""s together.
In another aspect of the invention, dummy wordlines are provided between gaps of blocks of memory cells to compensate for higher charge loss at higher stress temperatures exhibited at edge wordlines of blocks of memory cells having large gaps. Other methods include reducing the width of the edge wordlines, reducing the nitride thickness to make it less conducting in high temperatures or using different nitride types with less conductance in high temperatures. The dummy wordlines are typically ignored in normal operations on the memory.
In yet another aspect of the invention, dummy columns of memory cells formed during fabrication outside edge columns are connected to the actual used memory cells of sectors or the like. The columns of dummy memory cells are compensated by floating the dummy memory cells during normal programming and erase cycles, or alternatively, by programming and erasing the dummy memory cells along with the actual used memory cells in the sector. By treating the dummy memory cells similar to the actual used cells, charge that leaks into the dummy cells during fabrication and normal operation that has deleterious effects at higher stress temperatures and/or due to the longevity of customer operation is substantially eliminated.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.